seiko epson corporation 1 pf991-02 E0C6S48 4-bit single chip microcomputer l core cpu architecture l dot matrix lcd driver l programmable svd circuit/sound generator n description the E0C6S48 is a single-chip microcomputer made up of the 4-bit core cpu e0c6200, rom, ram, dot matrix lcd driver, input ports, output ports, i/o ports, clock timer, stopwatch timer, programmable timer, clock-syn- chronized serial interface, sound generator and watchdog timer. the E0C6S48 is most suitable for applications with equipment dot matrix display functions such as a highly functional electronic notebook. n features l cmos lsi 4-bit parallel processing l oscillation circuit ................................... osc1 : 32.768khz (typ.) crystal or cr oscillation circuit ( * 1) osc3 : 2mhz (max.) cr or ceramic oscillation circuit ( * 1) l instruction set ........................................ 108 instructions l instruction execution time ..................... 32.768khz : 152.6sec, 213.6sec, 366.2sec (depending on the instruction) 1mhz : 5.0sec, 7.0sec, 12.0sec 2mhz : 2.5sec, 3.5sec, 6.0sec l rom capacity ....................................... 8,192 words 12 bits l ram capacity ........................................ data memory : 768 words 4 bits display memory : 204 words 4 bits l input port ............................................... 8 bits (pull-up resistors may be supplemented * 1) l output port ............................................ 20 bits (buzzer and clock outputs are possible * 1) l i/o port .................................................. 16 bits l serial interface ...................................... 8-bit clock synchronous system 1 ch. l dot matrix type lcd driver ................... 51 segments 16 or 8 commons ( * 2) l time base counter ................................ clock timer, stopwatch timer l programmable timer ............................. 8-bit timer 1 ch., with event counter and clock output functions l watchdog timer ..................................... built-in l sound generator ................................... 8 programmable sounds (8 types of frequency) with envelope and 1-shot output functions l supply voltage detection (svd) ............ -2.2, -2.5, -3.1, -4.2v programmable (v dd standard) l interrupts ............................................... external : input port interrupt 2 systems internal : clock timer interrupt 1 system stopwatch timer interrupt 1 system programmable timer interrupt 1 system serial interface interrupt 1 system l power supply voltage ............................ 2.2v to 5.5v (min. 1.8v when the osc3 oscillation circuit is not used) l operating temperature range ............... -20c to 70c l current consumption (typ.) .................. halt mode : 32.768khz (crystal oscillation), 3.0v 2.5a operating mode : 32.768khz (crystal oscillation), 3.0v 6.5a 2mhz (cr oscillation), 3.0v 1ma l package ................................................ qfp8-144pin (plastic) or chip * 1: can be selected with mask option * 2: can be selected with software wide voltage operation products
2 E0C6S48 n block diagram osc1 osc2 osc3 osc4 com0~15 seg0~50 v dd v l1 ~v l5 ca~cf v ref v s1 v ss r00~r03 r10~r13 r20~r23 r30~r32 r33(srdy/ptclk) r40(fout) r41 r42(bz/fout) r43(bz) k00~k03 k10~k13 test sin sout sclk reset p00~p03 p10~p13 p20~p23 p30~p33 core cpu e0c6200 rom 8,192 words 12 bits system reset control interrupt generator ram 768 words 4 bits osc lcd driver 51 seg 16 com power controller svd sound generator output port clock timer watchdog timer stopwatch timer programmable timer/counter input port serial interface i/o port
3 E0C6S48 n pin configuration n pin description pin name v dd v ss v s1 v l1 ? l5 v ref ca?f osc1 osc2 osc3 osc4 com0?om15 seg0?eg50 k00?03 k10?13 p00?03 p10?13 p20?23 p30?33 r00?03 r10?13 r20?23 r30?32 r33 r40 r41 r42 r43 sin sout sclk reset test function power supply (+) power supply (-) internal logic system/oscillation system regulated voltage output lcd system power supply 1/4 bias generated internally, 1/5 bias generated externally * 1 lcd system power test pin * 2 lcd system voltage booster condenser connecting pin crystal or cr oscillator input * 1 crystal or cr oscillator output * 1 , c d buiil-in cr or ceramic oscillator input * 1 cr or ceramic oscillator output * 1 lcd common output (1/8 duty or 1/16 duty is selected on software) lcd segment output input port (pull up resistor is available by mask option) * 1 input port (pull up resistor is available by mask option) * 1 i/o port i/o port i/o port i/o port or output port * 1 output port output port output port output port output port, srdy output or ptclk output * 1 output port or fout output * 1 output port output port, bz output or fout output * 1 output port or bz output * 1 serial interface data input serial interface data output serial interface clock input/output initial reset input terminal testing input terminal * 3 pin no. 134 125 130 136?40 135 2, 1, 144?41 132 131 129 128 4?8, 20 74?1, 49?7, 34?1 87?5, 83 82?9 104?01 100?8, 96 95?2 91?8 124?21 120?17 116?13 112?10 109 108 107 106 105 78 77 76 126 127 i/o o i o i o o o i i i/o i/o i/o i/o o o o o o o o o o i o i/o i i complementary output or nch open drain output * 1 * 1 * 2 * 3 selected by mask option leave the v ref pin unconnected (n.c.). the test pin is used when the ic load is being detected. during ordinary operation be certain to connect this pin to v dd . qfp8-144pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 cb ca n.c. com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 n.c. com15 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 no. pin name 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 seg41 seg40 seg39 seg38 seg37 n.c. n.c. seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 n.c. seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 no. pin name 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 n.c. sclk sout sin k13 k12 k11 k10 k03 n.c. k02 k01 k00 no. pin name 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 r13 r12 r11 r10 r03 r02 r01 r00 v ss reset test osc4 osc3 v s1 osc2 osc1 n.c. v dd v ref v l1 v l2 v l3 v l4 v l5 cf ce cd cc no. pin name 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 p33 p32 p31 p30 p23 p22 p21 p20 p13 n.c. p12 p11 p10 p03 p02 p01 p00 r43 r42 r41 r40 r33 r32 r31 r30 r23 r22 r21 r20 n.c. = no connection no. pin name 73 108 37 72 index 36 1 144 109 E0C6S48
4 E0C6S48 n electrical characteristics l absolute maximum ratings rating supply voltage input voltage ( 1 ) input voltage ( 2 ) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 electrostatic proof pressure * 1: * 2: ( v dd =0v ) symbol v ss v i v iosc s i vss topr tstg tsol p d v e value -7.0 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec ( lead section ) 250 eiaj test method (c=200pf) 150v or more mil test method (c=100pf, r=1.5k w ) 900v or more unit v v v ma c c mw v the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package. l recommended operating conditions condition supply voltage oscillation frequency (1) oscillation frequency (2) oscillation frequency (3) voltage booster capacitor (1) voltage booster capacitor (2) voltage booster capacitor (3) capacitor between v dd and v l1 capacitor between v dd and v l2 capacitor between v dd and v l4 capacitor between v dd and v l5 capacitor between v dd and v s1 ( ta=-20 to 70 c ) symbol v ss f osc1 f osc3 f osc3 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 unit v v v khz khz khz f f f f f f f f max. -1.8 -2.2 -3.5 50 1,200 2,300 typ. -3.0 -3.0 -5.0 32.768 1,000 2,000 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 min. -3.8 -5.5 -5.5 20 50 50 remark v dd =0v vsc="1" vsc="2" vsc="0" vsc="1" vsc="2" l dc characteristics unit v v v v a a a ma ma ma ma a a a a (unless otherwise specified: v dd =0v,v ss =-3.0v,v l1 =-1.0v,v l2 =-2.0v,v l4 =-3.0v,v l5 =-4.0v,f osc1 =32.768khz,f osc3 =1mhz,ta=25 c,c 1 ? 8 =0.047 f) max. 0 0.8? ss 0 v ss +0.2 0.5 -15 0 -1.0 -2.0 -30 -10 typ. min. 0.2? ss v ss -0.2 v ss 0 -45 -0.5 2.0 4.0 30 10 characteristic high level input voltage low level input voltage high level input voltage low level input voltage high level input current low level input current (1) low level input current (2) high level output current (1) low level output current (1) high level output current (2) low level output current (2) common output current segment output current symbol v hin v lin v hin v lin i ih i il1 i il2 i oh1 i ol1 i oh2 i ol2 i oh3 i ol3 i oh4 i ol4 v ss =-2.2 to -5.5v ta=25 c v ss =-2.2 to -5.5v ta=25 c v ss =-3.0v v ih =0v v ss =-3.0v v il1 =v ss with pull-up resistor v ss =-3.0v v il2 =v ss no pull-up resistor v ss =-2.2v v oh1 =-0.5v v ss =-2.2v v ol1 =v ss +0.5v v ss =-2.2v v oh2 =-0.5v v ss =-2.2v v ol1 =v ss +0.5v v oh3 =-0.05v v ol3 =v l5 +0.05v v oh4 =-0.05v v ol4 =v l5 +0.05v condition k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset k00?3?0?3, p00?3?0?3 p20?23?0?3, sin, sclk reset p00?3?0?3?0?3?0?3 r00?3?0?3?0?3?0?3 r40?1, sout, sclk p00?3?0?3?0?3?0?3 r00?3?0?3?0?3?0?3 r40?1, sout, sclk r42?3 r42?3 com0?5 seg0?0
5 E0C6S48 l analog circuit characteristics and current consumption characteristic lcd drive voltage (normal mode) lcd drive voltage (heavy load protection mode) svd voltage svd circuit response time current consumption * 1 (osc1/crystal oscillation) current consumption * 1 (osc1/cr oscillation) * 1: symbol v l1 v l2 v l4 v l5 v l1 v l2 v l4 v l5 v svd0 v svd1 v svd2 v svd3 t svd i hlt i ex1 i ex2 i ex3 i hlt i ex1 i ex2 i ex3 unit v v v v v v v v v v v v s a a a a a a a a max. 1/2? l2 0.95 typ. 0.88 3/2? l2 0.95 2? l2 0.95 typ. 0.88 2? l1 0.90 3? l1 0.90 4? l1 0.90 -2.05 -2.30 -2.90 -3.90 100 5.0 9.0 600 1,500 70 80 600 1,500 typ. -1.80 -1.85 -1.90 -1.95 -2.01 -2.06 -2.11 -2.17 -2.22 -2.27 -2.32 -2.38 -2.43 -2.48 -2.53 -2.59 -0.92 -0.95 -0.97 -1.00 -1.03 -1.05 -1.08 -1.11 -1.13 -1.16 -1.18 -1.21 -1.24 -1.26 -1.29 -1.32 -2.20 -2.50 -3.10 -4.20 2.5 6.5 400 1,000 20 25 420 1,000 min. 1/2? l2 -0.1 typ. 1.12 3/2? l2 2? l2 typ. 1.12 2? l1 3? l1 4? l1 -2.35 -2.70 -3.30 -4.50 no panel loard. the svd circuit is in off status. condition connects a 1m w load resistance between v dd and v l1 ( no panel load ) connects a 1m w load resistance lc="0" between v dd and v l2 ( no panel load ) lc="1" lc="2" lc="3" lc="4" lc="5" lc="6" lc="7" lc="8" lc="9" lc="10" lc="11" lc="12" lc="13" lc="14" lc="15" connects a 1m w load resistance between v dd and v l4 ( no panel load ) connects a 1m w load resistance between v dd and v l5 ( no panel load ) connects a 1m w load resistance lc="0" between v dd and v l1 ( no panel load ) lc="1" lc="2" lc="3" lc="4" lc="5" lc="6" lc="7" lc="8" lc="9" lc="10" lc="11" lc="12" lc="13" lc="14" lc="15" connects a 1m w load resistance between v dd and v l2 ( no panel load ) connects a 1m w load resistance between v dd and v l4 ( no panel load ) connects a 1m w load resistance between v dd and v l5 ( no panel load ) svc="0" svc="1" svc="2" svc="3" during halt (vsc="0", oscc="0") during operation at 32khz (vsc="0", oscc="0") during operation at 1mhz (vsc="1") during operation at 2mhz (vsc="2", v ss =-5.0v) during halt (vsc="0" or "1", oscc="0") during operation at f osc1 ( vsc="0" or "1", oscc="0" ) during operation at 1mhz (vsc="1") during operation at 2mhz (vsc="2", v ss =-5.0v) (unless otherwise specified: v dd =0v,v ss =-3.0v,v l1 =-1.0v,v l2 =-2.0v,v l4 =-3.0v,v l5 =-4.0v,f osc1 =32.768khz,f osc3 =1mhz,ta=25 c,c 1 ? 8 =0.047 f)
6 E0C6S48 l ac characteristics reset input characteristic reset input time symbol t sr unit ms max. typ. min. 2.0 (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, v ih =0.5v ss , v il =0.9v ss ) reset t sr v il v ih power-on reset characteristic operating power voltage reset input time symbol vsr t psr unit v ms max. typ. min. -2.2 2.0 (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c) v dd reset v ss * 1 * 2 * 1 because the potential of the reset terminal not reached v dd level or higher. * 2 built-in pull-up resistor |v ss | reset t psr vsr v ih v il power on l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. osc1 crystal oscillation circuit characteristic oscillation start time built-in drain capacitance frequency/voltage deviation frequency/ic deviation frequency adjustable range harmonic oscillation start voltage permitted leak resistance symbol t sta c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak unit s pf pf ppm ppm ppm v m w max. 5 5 10 -5.5 typ. 20 19 45 min. -10 35 200 condition v ss =-2.2 to -5.5v package as assembled bare chip v ss =-2.2 to -5.5v c g =5 to 25pf c g =5pf ( v ss ) between osc1 and v dd, v s1 (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r(c i =35k w ), c gx =25pf, c dx =built-in, rfx=10m w , ta=25 c, vsc="0") osc1 cr oscillation circuit characteristic oscillation frequency oscillation start time frequency/voltage deviation symbol f osc1 t sta ? f/ ? v unit khz ms % max. typ. 130% 10 +5 typ. 32 min. typ. 70% -5 condition r cr1 =1.6m w v ss =-2.2 to -5.5v v ss =-2.2 to -5.5v (unless otherwise specified: v dd =0v, v ss =-3.0v, ta=25 c, vsc="0" or "1")
7 E0C6S48 osc3 cr oscillation circuit (1) characteristic oscillation frequency oscillation start time frequency/voltage deviation symbol f osc3 t sta ? f/ ? v unit khz ms % max. typ. 130% 10 +5 typ. 1,000 min. typ. 70% -5 condition r cr2 =60k w v ss =-2.2 to -5.5v v ss =-2.2 to -5.5v (unless otherwise specified: v dd =0v, v ss =-3.0v, ta=25 c, vsc="1") osc3 cr oscillation circuit (2) characteristic oscillation frequency oscillation start time frequency/voltage deviation symbol f osc3 t sta ? f/ ? v unit mhz ms % max. typ. 130% 10 +5 typ. 2.0 min. typ. 70% -5 condition r cr2 =30k w v ss =-3.5 to -5.5v v ss =-3.5 to -5.5v (unless otherwise specified: v dd =0v, v ss =-5.0v, ta=25 c, vsc="2") osc3 ceramic oscillation circuit (1) characteristic oscillation start time frequency/voltage deviation * 1: symbol t sta ? f/ ? v unit ms % max. 10 +3 typ. min. -3 made by murata mfg. co. condition v ss =-2.2 to -5.5v v ss =-2.2 to -5.5v (unless otherwise specified: v dd =0v, v ss =-3.0v, ta=25 c, vsc="1", ceramic oscillator: csb 1000j * 1 (1mhz), c gc =c dc =100pf, rfc=1m w ) osc3 ceramic oscillation circuit (2) characteristic oscillation start time frequency/voltage deviation * 1: symbol t sta ? f/ ? v unit ms % max. 10 +3 typ. min. -3 made by murata mfg. co. condition v ss =-3.5 to -5.5v v ss =-3.5 to -5.5v (unless otherwise specified: v dd =0v, v ss =-5.0v, ta=25 c, vsc="2", ceramic oscillator: csa 2.00mg * 1 (2mhz), c gc =c dc =100pf, rfc=1m w ) osc3 cr oscillation frequency - reference characteristics 10k 20k 50k 100k 200k 200k 100k 500k 5m 1m 2m resistance for cr oscillation r cr2 [ w ] cr oscillation frequency f osc3 [hz] 30k 40k 500k v dd = 0v v ss = -3.0v vsc = "1" ta = 25 c typ. value reference 10k 20k 50k 100k 200k 200k 100k 500k 5m 1m 2m resistance for cr oscillation r cr2 [ w ] cr oscillation frequency f osc3 [hz] 30k 40k 500k v dd = 0v v ss = -5.0v vsc = "2" ta = 25 c typ. value reference
E0C6S48 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 + sin sout sclk r00?03 r10?13 r20?23 r30?33 r40 r41 r42 r43 v ref v ss reset test v dd p00?03 p10?13 p20?23 p30?33 k00?03 k10?13 serial device lcd panel 51 16 output data i/o data input data cf ae ad cc cb ca v l5 v l4 v l3 v l2 v l1 v s1 osc4 ocs3 osc2 osc1 rfx x'tal ceramic rfc r cr1 mask option r cr2 c gx c gc c dc c 3 c 2 c 1 c 7 c 6 c 5 c 4 c 8 buzzer fout power 3? v n.c. E0C6S48 seg0 | seg50 com0 | com15 [the potential of the substrate (back of the chip) is v dd .] x'tal rfx c gx (r cr1 ) ceramic rfc c gc c dc (r cr2 ) crystal oscillator feedback resistor trimmer capacitor resistor for osc1 cr oscillation ceramic oscillator feedback resistor gate capacitor drain capacitor resistor for osc3 cr oscillation 32.768 khz, c i (max)=35 k w 10 m w 5?5 pf 1.6 m w (32 khz typ.) 500 khz? mhz 1 m w 100 pf 100 pf 20 k w ?00 k w (vsc=2) 40 k w ?00 k w (vsc=1) c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 booster capacitor (1) booster capacitor (2) booster capacitor (3) capacitor between v dd and v l1 capacitor between v dd and v l2 capacitor between v dd and v l4 capacitor between v dd and v l5 capacitor between v dd and v s1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f * 1 0.1 f n basic external connection diagram * 1 when the load on the liquid crystal system is large, increase the capacitance of the voltage booster capacitors (c 1 Cc 3 ) and the capacitors between v dd and liquid crystal system power (c 4 Cc 7 ). note: the above table is simply an example, and is not guaranteed to work.
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